TSMC has started producing chips at its Fab 21 near Phoenix, Arizona, using its 4nm-class process technology, Commerce Secretary Gina Raimondo told Reuters. This marks the first time such a cutting-edge production node has been manufactured in the United States. The confirmation from a high-ranking official comes months after the first unofficial information emerged that the fab was mass-producing chips for Apple.
“For the first time ever in our country’s history, we are making leading-edge 4nm chips on American soil, American workers — on par in yield and quality with Taiwan,” Raimondo told Reuters.
According to unofficial information, TSMC’s Fab 21 in Arizona is manufacturing at least three processor models: the A16 Bionic system-on-chip used in Apple’s iPhone 15 and iPhone 15 Plus; the main processor of Apple’s S9 system-in-package for smartwatches, which has two 64-bit cores and a quad-core neural engine; and an AMD Ryzen 9000-series CPU. These chips are produced on TSMC’s 4nm-class—N4 and N4P—process technologies.
The TSMC Arizona project is instrumental to the U.S. goal of producing 20% of the world’s most advanced logic chips by 2030, which the Biden administration set a few years ago before enacting the CHIPS and Science Act. TSMC’s Fab 21 in Arizona produces chips for American companies in volumes (it is rumored that currently, the facility’s production capacity is around 10,000 wafer starts per month), clear evidence that the initiative works.
Under the CHIPS and Science Act, the U.S. Commerce Department provided TSMC with $6.6 billion in grants and up to $5 billion in loan guarantees. The Fab 21 site will require funding of about $65 billion to include three fab modules that are set to be constructed and launched online by the end of the decade.
The first Fab 21 phase 1 module will officially start mass production using 4nm and 5nm-class process technologies. The next Fab 21 phase 2 is expected to follow in 2028 with 3nm-class process technologies. By the decade’s end, TSMC expects to build its Fab 21 phase 3, which will produce chips on 2nm-class and 1.6nm-class nodes and their variations with backside power delivery.